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use published versions, doc up, update CHANGELOG

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This commit is contained in:
Jorge Aparicio
2018-05-12 20:41:42 +02:00
parent 3a4a5be709
commit 0f139c386b
24 changed files with 548 additions and 555 deletions
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39
examples/itm.rs
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@@ -1,11 +1,13 @@
//! Sends "Hello, world!" through the ITM port 0
//!
//! **IMPORTANT** Not all Cortex-M chips support ITM. You'll have to connect the microcontroller's
//! SWO pin to the SWD interface. Note that some development boards don't provide this option.
//!
//! ITM is much faster than semihosting. Like 4 orders of magnitude or so.
//!
//! You'll need [`itmdump`] to receive the message on the host plus you'll need to uncomment the
//! **NOTE** Cortex-M0 chips don't support ITM.
//!
//! You'll have to connect the microcontroller's SWO pin to the SWD interface. Note that some
//! development boards don't provide this option.
//!
//! You'll need [`itmdump`] to receive the message on the host plus you'll need to uncomment two
//! `monitor` commands in the `.gdbinit` file.
//!
//! [`itmdump`]: https://docs.rs/itm/0.2.1/itm/
@@ -19,37 +21,34 @@
extern crate cortex_m;
#[macro_use]
extern crate cortex_m_rt as rt;
extern crate panic_abort; // panicking behavior
extern crate panic_semihosting;
use cortex_m::{asm, Peripherals};
use rt::ExceptionFrame;
main!(main);
entry!(main);
#[inline(always)]
fn main() -> ! {
let mut p = Peripherals::take().unwrap();
let stim = &mut p.ITM.stim[0];
iprintln!(stim, "Hello, world!");
loop {}
loop {
asm::bkpt();
}
}
exception!(DefaultHandler, dh);
// define the hard fault handler
exception!(HardFault, hard_fault);
#[inline(always)]
fn dh(_nr: u8) {
asm::bkpt();
fn hard_fault(ef: &ExceptionFrame) -> ! {
panic!("HardFault at {:#?}", ef);
}
exception!(HardFault, hf);
// define the default exception handler
exception!(*, default_handler);
#[inline(always)]
fn hf(_ef: &ExceptionFrame) -> ! {
asm::bkpt();
loop {}
fn default_handler(irqn: i16) {
panic!("Unhandled exception (IRQn = {})", irqn);
}
interrupts!(DefaultHandler);