From e6dabb3c34e8b3f0a4e9a8fa12376abf4951b2f6 Mon Sep 17 00:00:00 2001
From: Jorge Aparicio <jorge@japaric.io>
Date: Mon, 24 Sep 2018 03:55:52 +0200
Subject: [PATCH 1/2] try to break at `main`

the symbol is now stable. However, in optimized build it may be inlined into
Reset
---
 openocd.gdb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/openocd.gdb b/openocd.gdb
index 55cf8ac..f8cb5df 100644
--- a/openocd.gdb
+++ b/openocd.gdb
@@ -8,6 +8,9 @@ break DefaultHandler
 break UserHardFault
 break rust_begin_unwind
 
+# *try* to stop at the user entry point (it might be gone due to inlining)
+break main
+
 monitor arm semihosting enable
 
 load

From 69700e1438af2e0b4cc30d50ac96af6d6dd8cb0b Mon Sep 17 00:00:00 2001
From: Jorge Aparicio <jorge@japaric.io>
Date: Mon, 24 Sep 2018 03:56:39 +0200
Subject: [PATCH 2/2] add commented out ITM configuration

this got lost in a previous commit
---
 openocd.gdb | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/openocd.gdb b/openocd.gdb
index f8cb5df..100408e 100644
--- a/openocd.gdb
+++ b/openocd.gdb
@@ -13,6 +13,19 @@ break main
 
 monitor arm semihosting enable
 
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 8000000 must match the core clock frequency
+# monitor tpiu config internal itm.txt uart off 8000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 8000000 must match the core clock frequency
+# # 2000000 is the frequency of the SWO pin
+# monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
+# monitor itm port 0 on
+
 load
 
 # start the process but immediately halt the processor