diff --git a/openocd.gdb b/openocd.gdb
index f8cb5df..100408e 100644
--- a/openocd.gdb
+++ b/openocd.gdb
@@ -13,6 +13,19 @@ break main
 
 monitor arm semihosting enable
 
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 8000000 must match the core clock frequency
+# monitor tpiu config internal itm.txt uart off 8000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 8000000 must match the core clock frequency
+# # 2000000 is the frequency of the SWO pin
+# monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
+# monitor itm port 0 on
+
 load
 
 # start the process but immediately halt the processor