Blinky STM32F3-DISCOVERY

.cargo/config.toml

@@ -1,13 +1,13 @@
 [target.thumbv7m-none-eabi]
 # uncomment this to make `cargo run` execute programs on QEMU
-# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
+runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
 
 [target.'cfg(all(target_arch = "arm", target_os = "none"))']
 # uncomment ONE of these three option to make `cargo run` start a GDB session
 # which option to pick depends on your system
 # runner = "arm-none-eabi-gdb -q -x openocd.gdb"
 # runner = "gdb-multiarch -q -x openocd.gdb"
-# runner = "gdb -q -x openocd.gdb"
+runner = "gdb -q -x openocd.gdb"
 
 rustflags = [
   # Previously, the linker arguments --nmagic and -Tlink.x were set here.
@@ -29,9 +29,9 @@ rustflags = [
 [build]
 # Pick ONE of these default compilation targets
 # target = "thumbv6m-none-eabi"        # Cortex-M0 and Cortex-M0+
-target = "thumbv7m-none-eabi"        # Cortex-M3
+# target = "thumbv7m-none-eabi" # Cortex-M3
 # target = "thumbv7em-none-eabi"       # Cortex-M4 and Cortex-M7 (no FPU)
-# target = "thumbv7em-none-eabihf"     # Cortex-M4F and Cortex-M7F (with FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
 # target = "thumbv8m.base-none-eabi"   # Cortex-M23
 # target = "thumbv8m.main-none-eabi"   # Cortex-M33 (no FPU)
 # target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU)

Cargo.toml

@@ -1,8 +1,8 @@
 [package]
-authors = ["{{authors}}"]
+authors = ["jasper"]
 edition = "2018"
 readme = "README.md"
-name = "{{project-name}}"
+name = "embedded-rs"
 version = "0.1.0"
 
 [dependencies]
@@ -10,6 +10,7 @@ cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7"
 cortex-m-semihosting = "0.5"
 panic-halt = "1.0.0"
+# stm32f3 = "0.7.1"
 
 # Uncomment for the panic example.
 # panic-itm = "0.4.1"
@@ -20,13 +21,13 @@ panic-halt = "1.0.0"
 # Uncomment for the device example.
 # Update `memory.x`, set target to `thumbv7em-none-eabihf` in `.cargo/config`,
 # and then use `cargo build --example device` to build it.
-# [dependencies.stm32f3]
+[dependencies.stm32f3]
-# features = ["stm32f303", "rt"]
+features = ["stm32f303", "rt"]
-# version = "0.7.1"
+version = "^0.16.0"
 
 # this lets you use `cargo fix`!
 [[bin]]
-name = "{{project-name}}"
+name = "embedded-rs"
 test = false
 bench = false
 

examples/hello.rs

@@ -14,7 +14,7 @@ fn main() -> ! {
 
     // exit QEMU
     // NOTE do not run this on hardware; it can corrupt OpenOCD state
-    debug::exit(debug::EXIT_SUCCESS);
+    // debug::exit(debug::EXIT_SUCCESS);
 
     loop {}
 }

flake.nix

@@ -0,0 +1,41 @@
+# Adapted from https://wiki.nixos.org/wiki/Rust#Installation_via_rustup
+{
+  inputs = {
+    nixpkgs.url = "github:NixOS/nixpkgs/nixos-25.05";
+    flake-utils.url = "github:numtide/flake-utils";
+  };
+  outputs =
+    {
+      nixpkgs,
+      flake-utils,
+      ...
+    }:
+    flake-utils.lib.eachDefaultSystem (
+      system:
+      let
+        pkgs = import nixpkgs {
+          inherit system;
+        };
+      in
+      with pkgs;
+      {
+        devShells.default = mkShell {
+          strictDeps = true;
+          nativeBuildInputs = [
+            rustup
+            rustPlatform.bindgenHook
+            pkg-config
+          ];
+          buildInputs = [
+            # Libraries here
+            openssl
+            openocd
+          ];
+          RUSTC_VERSION = "stable";
+          shellHook = ''
+            export PATH="''${RUSTUP_HOME:-~/.rustup}/toolchains/$RUSTC_VERSION-${stdenv.hostPlatform.rust.rustcTarget}/bin:''${CARGO_HOME:-~/.cargo}/bin:$PATH"
+          '';
+        };
+      }
+    );
+}

memory.x

@@ -3,8 +3,8 @@ MEMORY
   /* NOTE 1 K = 1 KiBi = 1024 bytes */
   /* TODO Adjust these memory regions to match your device memory layout */
   /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */
-  FLASH : ORIGIN = 0x00000000, LENGTH = 256K
+  FLASH : ORIGIN = 0x08000000, LENGTH = 256K
-  RAM : ORIGIN = 0x20000000, LENGTH = 64K
+  RAM : ORIGIN = 0x20000000, LENGTH = 40K
 }
 
 /* This is where the call stack will be allocated. */

openocd.gdb

@@ -36,5 +36,5 @@ monitor arm semihosting enable
 
 load
 
-# start the process but immediately halt the processor
+# Run to main
-stepi
+continue

src/main.rs

@@ -3,15 +3,49 @@
 
 // pick a panicking behavior
 use panic_halt as _; // you can put a breakpoint on `rust_begin_unwind` to catch panics
-// use panic_abort as _; // requires nightly
+                     // use panic_abort as _; // requires nightly
-// use panic_itm as _; // logs messages over ITM; requires ITM support
+                     // use panic_itm as _; // logs messages over ITM; requires ITM support
-// use panic_semihosting as _; // logs messages to the host stderr; requires a debugger
+                     // use panic_semihosting as _; // logs messages to the host stderr; requires a debugger
 
+use cortex_m::peripheral::{syst, Peripherals};
 use cortex_m_rt::entry;
 
+use stm32f3::stm32f303;
+
 #[entry]
 fn main() -> ! {
+    let cortex_peripherals = Peripherals::take().unwrap();
+    let mut systick = cortex_peripherals.SYST;
+    systick.set_clock_source(syst::SystClkSource::Core);
+    systick.set_reload(8_000_000); // 1s
+    systick.clear_current();
+
+    let device_peripherals = stm32f303::Peripherals::take().unwrap();
+    let rcc = device_peripherals.RCC;
+    rcc.ahbenr().write(|w| w.iopeen().set_bit());
+    // PE9: LD3 (red)
+    // PE8: LD4 (blue)
+    // PE10: LD5 (orange)
+    let gpioe = device_peripherals.GPIOE;
+    gpioe
+        .moder()
+        .write(|w| w.moder9().output().moder8().output().moder10().output());
+    gpioe.bsrr().write(|w| w.bs9().set_bit());
+    gpioe.bsrr().write(|w| w.bs8().set_bit());
+    gpioe.bsrr().write(|w| w.bs10().set_bit());
+
+    systick.enable_counter();
+    let mut enabled = true;
     loop {
-        // your code goes here
+        while !systick.has_wrapped() {}
+        enabled = !enabled;
+        gpioe.odr().write(|w| {
+            w.odr8()
+                .bit(enabled)
+                .odr9()
+                .bit(enabled)
+                .odr10()
+                .bit(enabled)
+        });
     }
 }