backport fixes from the book plus other small updates

This commit is contained in:
Jorge Aparicio
2018-09-13 21:40:25 +02:00
parent 7faeedd95a
commit 9facab2960
3 changed files with 17 additions and 15 deletions

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@@ -3,9 +3,11 @@
# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel" # runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
[target.'cfg(all(target_arch = "arm", target_os = "none"))'] [target.'cfg(all(target_arch = "arm", target_os = "none"))']
# uncomment this to make `cargo run` start a GDB session # uncomment ONE of these three option to make `cargo run` start a GDB session
# NOTE: you may need to change `arm-none-eabi-gdb` # which option to pick depends on your system
# runner = "arm-none-eabi-gdb -x openocd.gdb" # runner = "arm-none-eabi-gdb -x openocd.gdb"
# runner = "gdb-multiarch -x openocd.gdb"
# runner = "gdb -x openocd.gdb"
rustflags = [ rustflags = [
# LLD (shipped with the Rust toolchain) is used as the default linker # LLD (shipped with the Rust toolchain) is used as the default linker

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@@ -1,9 +1,6 @@
# TODO remove
cargo-features = ["edition"]
[package] [package]
edition = "2018"
authors = ["{{authors}}"] authors = ["{{authors}}"]
edition = "2018"
name = "{{project-name}}" name = "{{project-name}}"
version = "0.1.0" version = "0.1.0"
@@ -14,7 +11,7 @@ cortex-m-semihosting = "0.3.1"
panic-halt = "0.1.3" panic-halt = "0.1.3"
# Uncomment for the panic example. # Uncomment for the panic example.
# panic-itm = "0.3.0" # panic-itm = "0.4.0"
# Uncomment for the allocator example. # Uncomment for the allocator example.
# alloc-cortex-m = "0.3.5" # alloc-cortex-m = "0.3.5"

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@@ -8,9 +8,11 @@ This project is developed and maintained by the [Cortex-M team][team].
To build embedded programs using this template you'll need: To build embedded programs using this template you'll need:
- Rust 1.30-beta or nightly. `rustup default beta` - Rust 1.30, 1.30-beta, nightly-2018-09-13 or a newer toolchain. e.g. `rustup
default beta`
- The `cargo generate` subcommand: `cargo install cargo-generate` - The `cargo generate` subcommand. [Installation
instructions](https://github.com/ashleygwilliams/cargo-generate#installation).
- `rust-std` components (pre-compiled `core` crate) for the ARM Cortex-M - `rust-std` components (pre-compiled `core` crate) for the ARM Cortex-M
targets. Run: targets. Run:
@@ -22,9 +24,10 @@ $ rustup target add thumbv6m-none-eabi thumbv7m-none-eabi thumbv7em-none-eabi th
## Using this template ## Using this template
**NOTE**: This is the very short version that only covers building programs. For **NOTE**: This is the very short version that only covers building programs. For
the long version check [the embedded Rust book][book]. the long version, which additionally covers flashing, running and debugging
programs, check [the embedded Rust book][book].
[book]: https://rust-embedded.github.io/book/blinky/blinky.html [book]: http://book.rust-embedded.org
0. Before we begin you need to identify some characteristics of the target 0. Before we begin you need to identify some characteristics of the target
device as these will be used to configure the project: device as these will be used to configure the project:
@@ -33,7 +36,8 @@ the long version check [the embedded Rust book][book].
- Does the ARM core include an FPU? Cortex-M4**F** and Cortex-M7**F** cores do. - Does the ARM core include an FPU? Cortex-M4**F** and Cortex-M7**F** cores do.
- How much Flash memory and RAM does the target device has? e.g. 40 KB of RAM - How much Flash memory and RAM does the target device has? e.g. 256 KiB of
Flash and 32 KiB of RAM.
- Where are Flash memory and RAM mapped in the address space? e.g. RAM is - Where are Flash memory and RAM mapped in the address space? e.g. RAM is
commonly located at address `0x2000_0000`. commonly located at address `0x2000_0000`.
@@ -46,9 +50,9 @@ STM32F303VCT6 microcontroller. This microcontroller has:
- A Cortex-M4F core that includes a single precision FPU - A Cortex-M4F core that includes a single precision FPU
- 256 KB of Flash located at address 0x0800_0000. - 256 KiB of Flash located at address 0x0800_0000.
- 40 KB of RAM located at address 0x2000_0000. (There's another RAM region but - 40 KiB of RAM located at address 0x2000_0000. (There's another RAM region but
for simplicity we'll ignore it). for simplicity we'll ignore it).
1. Instantiate the template. 1. Instantiate the template.
@@ -66,7 +70,6 @@ $ cd app
bottom of `.cargo/config`. For the STM32F303VCT6, which has a Cortex-M4F bottom of `.cargo/config`. For the STM32F303VCT6, which has a Cortex-M4F
core, we'll pick the `thumbv7em-none-eabihf` target. core, we'll pick the `thumbv7em-none-eabihf` target.
``` console ``` console
$ tail -n6 .cargo/config $ tail -n6 .cargo/config
``` ```