update examples and docs
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@@ -1,12 +1,12 @@
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//! Using a device crate
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//!
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//! Crates generated using [`svd2rust`] are referred to as device crates. These crates provides an
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//! API to access the peripherals of a device. When you depend on one of these crates and the "rt"
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//! feature is enabled you don't need link to the cortex-m-rt crate.
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//! API to access the peripherals of a device.
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//!
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//! [`svd2rust`]: https://crates.io/crates/svd2rust
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//!
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//! Device crates also provide an `interrupt!` macro to register interrupt handlers.
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//! Device crates also provide an `interrupt!` macro (behind the "rt" feature) to register interrupt
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//! handlers.
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//!
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//! This example depends on the [`stm32f103xx`] crate so you'll have to add it to your Cargo.toml.
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//!
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@@ -16,80 +16,82 @@
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//! $ edit Cargo.toml && tail $_
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//! [dependencies.stm32f103xx]
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//! features = ["rt"]
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//! version = "0.9.0"
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//! version = "0.10.0"
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//! ```
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//!
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//! The `stm32f103xx` crate provides an `interrupts.x` file so you must remove the one in the root
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//! of this crate.
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//!
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//! ---
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#![deny(warnings)]
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#![feature(const_fn)]
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#![no_main]
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#![no_std]
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extern crate cortex_m;
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// extern crate cortex_m_rt; // included in the device crate
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extern crate cortex_m_semihosting;
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#[macro_use(exception, interrupt)]
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#[macro_use]
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extern crate cortex_m_rt as rt;
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extern crate cortex_m_semihosting as sh;
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#[macro_use]
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extern crate stm32f103xx;
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extern crate panic_abort; // panicking behavior
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extern crate panic_abort;
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use core::cell::RefCell;
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use core::fmt::Write;
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use cortex_m::interrupt::{self, Mutex};
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use cortex_m::asm;
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use cortex_m::peripheral::syst::SystClkSource;
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use cortex_m_semihosting::hio::{self, HStdout};
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use rt::ExceptionFrame;
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use sh::hio::{self, HStdout};
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use stm32f103xx::Interrupt;
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static HSTDOUT: Mutex<RefCell<Option<HStdout>>> = Mutex::new(RefCell::new(None));
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main!(main);
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static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> = Mutex::new(RefCell::new(None));
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fn main() -> ! {
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let p = cortex_m::Peripherals::take().unwrap();
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fn main() {
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let global_p = cortex_m::Peripherals::take().unwrap();
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interrupt::free(|cs| {
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let hstdout = HSTDOUT.borrow(cs);
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if let Ok(fd) = hio::hstdout() {
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*hstdout.borrow_mut() = Some(fd);
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}
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let mut syst = p.SYST;
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let mut nvic = p.NVIC;
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let mut nvic = global_p.NVIC;
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nvic.enable(Interrupt::TIM2);
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*NVIC.borrow(cs).borrow_mut() = Some(nvic);
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nvic.enable(Interrupt::EXTI0);
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let mut syst = global_p.SYST;
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syst.set_clock_source(SystClkSource::Core);
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syst.set_reload(8_000_000); // 1s
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syst.enable_counter();
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syst.enable_interrupt();
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});
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syst.set_clock_source(SystClkSource::Core);
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syst.set_reload(8_000_000); // 1s
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syst.enable_counter();
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loop {
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// busy wait until the timer wraps around
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while !syst.has_wrapped() {}
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// trigger the `EXTI0` interrupt
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nvic.set_pending(Interrupt::EXTI0);
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}
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}
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exception!(SYS_TICK, tick);
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interrupt!(EXTI0, exti0, state: Option<HStdout> = None);
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fn tick() {
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interrupt::free(|cs| {
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let hstdout = HSTDOUT.borrow(cs);
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if let Some(hstdout) = hstdout.borrow_mut().as_mut() {
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writeln!(*hstdout, "Tick").ok();
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}
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fn exti0(state: &mut Option<HStdout>) {
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if state.is_none() {
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*state = Some(hio::hstdout().unwrap());
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}
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if let Some(nvic) = NVIC.borrow(cs).borrow_mut().as_mut() {
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nvic.set_pending(Interrupt::TIM2);
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}
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});
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if let Some(hstdout) = state.as_mut() {
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hstdout.write_str(".").unwrap();
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}
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}
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interrupt!(TIM2, tock, locals: {
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tocks: u32 = 0;
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});
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exception!(DefaultHandler, deh);
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fn tock(l: &mut TIM2::Locals) {
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l.tocks += 1;
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interrupt::free(|cs| {
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let hstdout = HSTDOUT.borrow(cs);
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if let Some(hstdout) = hstdout.borrow_mut().as_mut() {
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writeln!(*hstdout, "Tock ({})", l.tocks).ok();
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}
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});
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#[inline(always)]
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fn deh(_nr: u8) {
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asm::bkpt();
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}
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exception!(HardFault, hf);
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#[inline(always)]
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fn hf(_ef: &ExceptionFrame) -> ! {
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asm::bkpt();
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loop {}
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}
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interrupts!(DefaultHandler);
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