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bump the cortex-m-rt to v0.4.0

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This commit is contained in:
Jorge Aparicio
2018-04-23 23:20:02 +02:00
parent 6f62705eaf
commit 2cd4ea31e5
23 changed files with 254 additions and 164 deletions
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28
.cargo/config
View File

@@ -2,34 +2,38 @@
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "linker=arm-none-eabi-ld",
"-Z", "linker-flavor=ld",
"-Z", "thinlto=no",
"-C", "linker=lld",
"-Z", "linker-flavor=ld.lld",
# "-C", "linker=arm-none-eabi-ld",
# "-Z", "linker-flavor=ld",
]
[target.thumbv7m-none-eabi]
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "linker=arm-none-eabi-ld",
"-Z", "linker-flavor=ld",
"-Z", "thinlto=no",
"-C", "linker=lld",
"-Z", "linker-flavor=ld.lld",
# "-C", "linker=arm-none-eabi-ld",
# "-Z", "linker-flavor=ld",
]
[target.thumbv7em-none-eabi]
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "linker=arm-none-eabi-ld",
"-Z", "linker-flavor=ld",
"-Z", "thinlto=no",
"-C", "linker=lld",
"-Z", "linker-flavor=ld.lld",
# "-C", "linker=arm-none-eabi-ld",
# "-Z", "linker-flavor=ld",
]
[target.thumbv7em-none-eabihf]
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "linker=arm-none-eabi-ld",
"-Z", "linker-flavor=ld",
"-Z", "thinlto=no",
"-C", "linker=lld",
"-Z", "linker-flavor=ld.lld",
# "-C", "linker=arm-none-eabi-ld",
# "-Z", "linker-flavor=ld",
]

43
.travis.yml Normal file
View File

@@ -0,0 +1,43 @@
language: rust
matrix:
include:
- env: TARGET=thumbv6m-none-eabi
rust: nightly
- env: TARGET=thumbv7m-none-eabi
rust: nightly
- env: TARGET=thumbv7em-none-eabi
rust: nightly
- env: TARGET=thumbv7em-none-eabihf
rust: nightly
before_install: set -e
install:
- bash ci/install.sh
script:
- bash ci/script.sh
after_script: set +e
after_success:
- bash ci/after_success.sh
cache: cargo
before_cache:
# Travis can't cache files that are not readable by "others"
- chmod -R a+r $HOME/.cargo
branches:
only:
- staging
- trying
notifications:
email:
on_success: never

9
CHANGELOG.md
View File

@@ -5,6 +5,12 @@ This project adheres to [Semantic Versioning](http://semver.org/).
## [Unreleased]
## [v0.2.7] - 2018-04-24
### Changed
- Bumped the dependency of `cortex-m-rt` to v0.4.0.
## [v0.2.6] - 2018-04-09
### Changed
@@ -143,7 +149,8 @@ This project adheres to [Semantic Versioning](http://semver.org/).
- Initial release
[Unreleased]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.6...HEAD
[Unreleased]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.7...HEAD
[v0.2.7]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.6...v0.2.7
[v0.2.6]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.5...v0.2.6
[v0.2.5]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.4...v0.2.5
[v0.2.4]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.3...v0.2.4

17
Cargo.toml
View File

@@ -6,25 +6,24 @@ keywords = ["arm", "cortex-m", "template"]
license = "MIT OR Apache-2.0"
name = "cortex-m-quickstart"
repository = "https://github.com/japaric/cortex-m-quickstart"
version = "0.2.6"
version = "0.2.7"
[dependencies]
cortex-m = "0.4.0"
cortex-m-rt = "0.4.0"
cortex-m-semihosting = "0.2.0"
# alloc-cortex-m release doesn't use linked_list_allocator v0.5.0 yet.
panic-abort = "0.1.1"
panic-semihosting = "0.1.0"
panic-itm = "0.1.0"
# Uncomment for the allocator example.
#alloc-cortex-m = "0.3.2"
[dependencies.cortex-m-rt]
version = "0.3.15"
# Comment for the panic example.
features = ["abort-on-panic"]
#alloc-cortex-m = "0.3.3"
# Uncomment for the device example.
# [dependencies.stm32f103xx]
# features = ["rt"]
# version = "0.8.0"
# version = "0.9.0"
[profile.release]
debug = true
lto = true
opt-level = "s"

2
LICENSE-MIT
View File

@@ -1,4 +1,4 @@
Copyright (c) 2017 {{toml-escape author}}
Copyright (c) 2018
Permission is hereby granted, free of charge, to any
person obtaining a copy of this software and associated

3
bors.toml Normal file
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@@ -0,0 +1,3 @@
status = [
"continuous-integration/travis-ci/push",
]

9
ci/install.sh Normal file
View File

@@ -0,0 +1,9 @@
set -euxo pipefail
main() {
rustup target add $TARGET
cargo install cargo-edit || true
}
main

57
ci/script.sh Normal file
View File

@@ -0,0 +1,57 @@
set -euxo pipefail
main() {
local td=$(mktemp -d)
git clone . $td
pushd $td
cat >memory.x <<'EOF'
MEMORY
{
/* NOTE K = KiBi = 1024 bytes */
FLASH : ORIGIN = 0x08000000, LENGTH = 256K
RAM : ORIGIN = 0x20000000, LENGTH = 40K
}
EOF
local examples=(
crash
# device
hello
itm
override-exception-handler
panic
)
for ex in "${examples[@]}"; do
cargo build --target $TARGET --example $ex
cargo build --target $TARGET --example $ex --release
done
cargo add alloc-cortex-m
cargo build --target $TARGET --example allocator
cargo build --target $TARGET --example allocator --release
examples+=( allocator )
if [ $TARGET = thumbv7m-none-eabi ]; then
cat >>Cargo.toml <<'EOF'
[dependencies.stm32f103xx]
features = ["rt"]
version = "0.9.0"
EOF
cargo build --target $TARGET --example device
cargo build --target $TARGET --example device --release
examples+=( device )
fi
IFS=,;eval arm-none-eabi-size target/$TARGET/release/examples/"{${examples[*]}}"
popd
rm -rf $td
}
main

14
examples/allocator.rs
View File

@@ -1,7 +1,6 @@
//! How to use the heap and a dynamic memory allocator
//!
//! This example depends on the alloc-cortex-m crate so you'll have to add it
//! to your Cargo.toml:
//! This example depends on the alloc-cortex-m crate so you'll have to add it to your Cargo.toml:
//!
//! ``` text
//! # or edit the Cargo.toml file manually
@@ -11,8 +10,8 @@
//! ---
#![feature(alloc)]
#![feature(used)]
#![feature(global_allocator)]
#![feature(used)]
#![no_std]
// This is the allocator crate; you can use a different one
@@ -22,26 +21,27 @@ extern crate alloc;
extern crate cortex_m;
extern crate cortex_m_rt;
extern crate cortex_m_semihosting;
extern crate panic_abort; // panicking behavior
use core::fmt::Write;
use alloc_cortex_m::CortexMHeap;
use cortex_m::asm;
use cortex_m_semihosting::hio;
use alloc_cortex_m::CortexMHeap;
#[global_allocator]
static ALLOCATOR: CortexMHeap = CortexMHeap::empty();
extern "C" {
static mut _sheap: u32;
static mut _eheap: u32;
}
const HEAP_SIZE: usize = 1024; // in bytes
fn main() {
// Initialize the allocator
let start = unsafe { &mut _sheap as *mut u32 as usize };
let end = unsafe { &mut _eheap as *mut u32 as usize };
unsafe { ALLOCATOR.init(start, end - start) }
unsafe { ALLOCATOR.init(start, HEAP_SIZE) }
// Growable array allocated on the heap
let xs = vec![0, 1, 2];

12
examples/crash.rs
View File

@@ -1,12 +1,11 @@
//! Debugging a crash (exception)
//!
//! The `cortex-m-rt` crate provides functionality for this through a default
//! exception handler. When an exception is hit, the default handler will
//! trigger a breakpoint and in this debugging context the stacked registers
//! are accessible.
//! The `cortex-m-rt` crate provides functionality for this through a default exception handler.
//! When an exception is hit, the default handler will trigger a breakpoint and in this debugging
//! context the stacked registers are accessible.
//!
//! In you run the example below, you'll be able to inspect the state of your
//! program under the debugger using these commands:
//! In you run the example below, you'll be able to inspect the state of your program under the
//! debugger using these commands:
//!
//! ``` text
//! (gdb) # Exception frame = program state during the crash
@@ -63,6 +62,7 @@
extern crate cortex_m;
extern crate cortex_m_rt;
extern crate panic_abort; // panicking behavior
use core::ptr;

25
examples/device.rs
View File

@@ -1,25 +1,22 @@
//! Using a device crate
//!
//! Crates generated using [`svd2rust`] are referred to as device crates. These
//! crates provides an API to access the peripherals of a device. When you
//! depend on one of these crates and the "rt" feature is enabled you don't need
//! link to the cortex-m-rt crate.
//! Crates generated using [`svd2rust`] are referred to as device crates. These crates provides an
//! API to access the peripherals of a device. When you depend on one of these crates and the "rt"
//! feature is enabled you don't need link to the cortex-m-rt crate.
//!
//! [`svd2rust`]: https://crates.io/crates/svd2rust
//!
//! Device crates also provide an `interrupt!` macro to register interrupt
//! handlers.
//! Device crates also provide an `interrupt!` macro to register interrupt handlers.
//!
//! This example depends on the [`stm32f103xx`] crate so you'll have to add it
//! to your Cargo.toml.
//! This example depends on the [`stm32f103xx`] crate so you'll have to add it to your Cargo.toml.
//!
//! [`stm32f103xx`]: https://crates.io/crates/stm32f103xx
//!
//! ```
//! $ edit Cargo.toml && cat $_
//! $ edit Cargo.toml && tail $_
//! [dependencies.stm32f103xx]
//! features = ["rt"]
//! version = "0.8.0"
//! version = "0.9.0"
//! ```
//!
//! ---
@@ -29,9 +26,11 @@
#![no_std]
extern crate cortex_m;
// extern crate cortex_m_rt; // included in the device crate
extern crate cortex_m_semihosting;
#[macro_use(exception, interrupt)]
extern crate stm32f103xx;
extern crate panic_abort; // panicking behavior
use core::cell::RefCell;
use core::fmt::Write;
@@ -41,11 +40,9 @@ use cortex_m::peripheral::syst::SystClkSource;
use cortex_m_semihosting::hio::{self, HStdout};
use stm32f103xx::Interrupt;
static HSTDOUT: Mutex<RefCell<Option<HStdout>>> =
Mutex::new(RefCell::new(None));
static HSTDOUT: Mutex<RefCell<Option<HStdout>>> = Mutex::new(RefCell::new(None));
static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> =
Mutex::new(RefCell::new(None));
static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> = Mutex::new(RefCell::new(None));
fn main() {
let global_p = cortex_m::Peripherals::take().unwrap();

1
examples/hello.rs
View File

@@ -8,6 +8,7 @@
extern crate cortex_m;
extern crate cortex_m_rt;
extern crate cortex_m_semihosting;
extern crate panic_abort; // panicking behavior
use core::fmt::Write;

15
examples/itm.rs
View File

@@ -1,15 +1,14 @@
//! Sends "Hello, world!" through the ITM port 0
//!
//! **IMPORTANT** Not all Cortex-M chips support ITM. You'll have to connect the
//! microcontroller's SWO pin to the SWD interface. Note that some development
//! boards don't provide this option.
//! **IMPORTANT** Not all Cortex-M chips support ITM. You'll have to connect the microcontroller's
//! SWO pin to the SWD interface. Note that some development boards don't provide this option.
//!
//! ITM is much faster than semihosting. Like 4 orders of magnitude or so.
//!
//! You'll need [`itmdump`] to receive the message on the host plus you'll need
//! to uncomment the `monitor` commands in the `.gdbinit` file.
//! You'll need [`itmdump`] to receive the message on the host plus you'll need to uncomment the
//! `monitor` commands in the `.gdbinit` file.
//!
//! [`itmdump`]: https://docs.rs/itm/0.1.1/itm/
//! [`itmdump`]: https://docs.rs/itm/0.2.1/itm/
//!
//! ---
@@ -19,6 +18,7 @@
#[macro_use]
extern crate cortex_m;
extern crate cortex_m_rt;
extern crate panic_itm; // panicking behavior
use cortex_m::{asm, Peripherals};
@@ -27,6 +27,9 @@ fn main() {
let mut itm = p.ITM;
iprintln!(&mut itm.stim[0], "Hello, world!");
// Also prints the panic message to the ITM
panic!("Oops");
}
// As we are not using interrupts, we just register a dummy catch all handler

4
examples/override-exception-handler.rs
View File

@@ -4,8 +4,7 @@
//!
//! [1]: https://docs.rs/cortex-m-rt/0.3.2/cortex_m_rt/macro.exception.html
//!
//! The default exception handler can be overridden using the
//! [`default_handler!`][2] macro
//! The default exception handler can be overridden using the [`default_handler!`][2] macro
//!
//! [2]: https://docs.rs/cortex-m-rt/0.3.2/cortex_m_rt/macro.default_handler.html
//!
@@ -17,6 +16,7 @@
extern crate cortex_m;
#[macro_use(exception)]
extern crate cortex_m_rt;
extern crate panic_abort; // panicking behavior
use core::ptr;

39
examples/panic.rs
View File

@@ -1,53 +1,26 @@
//! Defining the panic handler
//! Changing the panic handler
//!
//! The panic handler can be defined through the `panic_fmt` [language item][1].
//! Make sure that the "abort-on-panic" feature of the cortex-m-rt crate is
//! disabled to avoid redefining the language item.
//! The easiest way to change the panic handler is to use a different [panic implementation
//! crate][0].
//!
//! [1]: https://doc.rust-lang.org/unstable-book/language-features/lang-items.html
//! [0]: https://crates.io/keywords/panic-impl
//!
//! ---
#![feature(core_intrinsics)]
#![feature(lang_items)]
#![feature(used)]
#![no_std]
extern crate cortex_m;
extern crate cortex_m_rt;
extern crate cortex_m_semihosting;
use core::fmt::Write;
use core::intrinsics;
// extern crate panic_abort;
extern crate panic_semihosting; // reports panic messages to the host stderr using semihosting
use cortex_m::asm;
use cortex_m_semihosting::hio;
fn main() {
panic!("Oops");
}
#[lang = "panic_fmt"]
#[no_mangle]
pub unsafe extern "C" fn rust_begin_unwind(
args: core::fmt::Arguments,
file: &'static str,
line: u32,
col: u32,
) -> ! {
if let Ok(mut stdout) = hio::hstdout() {
write!(stdout, "panicked at '")
.and_then(|_| {
stdout
.write_fmt(args)
.and_then(|_| writeln!(stdout, "', {}:{}:{}", file, line, col))
})
.ok();
}
intrinsics::abort()
}
// As we are not using interrupts, we just register a dummy catch all handler
#[link_section = ".vector_table.interrupts"]
#[used]

1
src/examples/_0_hello.rs
View File

@@ -10,6 +10,7 @@
//! extern crate cortex_m;
//! extern crate cortex_m_rt;
//! extern crate cortex_m_semihosting;
//! extern crate panic_abort; // panicking behavior
//!
//! use core::fmt::Write;
//!

15
src/examples/_1_itm.rs
View File

@@ -1,15 +1,14 @@
//! Sends "Hello, world!" through the ITM port 0
//!
//! **IMPORTANT** Not all Cortex-M chips support ITM. You'll have to connect the
//! microcontroller's SWO pin to the SWD interface. Note that some development
//! boards don't provide this option.
//! **IMPORTANT** Not all Cortex-M chips support ITM. You'll have to connect the microcontroller's
//! SWO pin to the SWD interface. Note that some development boards don't provide this option.
//!
//! ITM is much faster than semihosting. Like 4 orders of magnitude or so.
//!
//! You'll need [`itmdump`] to receive the message on the host plus you'll need
//! to uncomment the `monitor` commands in the `.gdbinit` file.
//! You'll need [`itmdump`] to receive the message on the host plus you'll need to uncomment the
//! `monitor` commands in the `.gdbinit` file.
//!
//! [`itmdump`]: https://docs.rs/itm/0.1.1/itm/
//! [`itmdump`]: https://docs.rs/itm/0.2.1/itm/
//!
//! ---
//!
@@ -21,6 +20,7 @@
//! #[macro_use]
//! extern crate cortex_m;
//! extern crate cortex_m_rt;
//! extern crate panic_itm; // panicking behavior
//!
//! use cortex_m::{asm, Peripherals};
//!
@@ -29,6 +29,9 @@
//! let mut itm = p.ITM;
//!
//! iprintln!(&mut itm.stim[0], "Hello, world!");
//!
//! // Also prints the panic message to the ITM
//! panic!("Oops");
//! }
//!
//! // As we are not using interrupts, we just register a dummy catch all handler

39
src/examples/_2_panic.rs
View File

@@ -1,55 +1,28 @@
//! Defining the panic handler
//! Changing the panic handler
//!
//! The panic handler can be defined through the `panic_fmt` [language item][1].
//! Make sure that the "abort-on-panic" feature of the cortex-m-rt crate is
//! disabled to avoid redefining the language item.
//! The easiest way to change the panic handler is to use a different [panic implementation
//! crate][0].
//!
//! [1]: https://doc.rust-lang.org/unstable-book/language-features/lang-items.html
//! [0]: https://crates.io/keywords/panic-impl
//!
//! ---
//!
//! ```
//!
//! #![feature(core_intrinsics)]
//! #![feature(lang_items)]
//! #![feature(used)]
//! #![no_std]
//!
//! extern crate cortex_m;
//! extern crate cortex_m_rt;
//! extern crate cortex_m_semihosting;
//!
//! use core::fmt::Write;
//! use core::intrinsics;
//! // extern crate panic_abort;
//! extern crate panic_semihosting; // reports panic messages to the host stderr using semihosting
//!
//! use cortex_m::asm;
//! use cortex_m_semihosting::hio;
//!
//! fn main() {
//! panic!("Oops");
//! }
//!
//! #[lang = "panic_fmt"]
//! #[no_mangle]
//! pub unsafe extern "C" fn rust_begin_unwind(
//! args: core::fmt::Arguments,
//! file: &'static str,
//! line: u32,
//! col: u32,
//! ) -> ! {
//! if let Ok(mut stdout) = hio::hstdout() {
//! write!(stdout, "panicked at '")
//! .and_then(|_| {
//! stdout
//! .write_fmt(args)
//! .and_then(|_| writeln!(stdout, "', {}:{}:{}", file, line, col))
//! })
//! .ok();
//! }
//!
//! intrinsics::abort()
//! }
//!
//! // As we are not using interrupts, we just register a dummy catch all handler
//! #[link_section = ".vector_table.interrupts"]
//! #[used]

12
src/examples/_3_crash.rs
View File

@@ -1,12 +1,11 @@
//! Debugging a crash (exception)
//!
//! The `cortex-m-rt` crate provides functionality for this through a default
//! exception handler. When an exception is hit, the default handler will
//! trigger a breakpoint and in this debugging context the stacked registers
//! are accessible.
//! The `cortex-m-rt` crate provides functionality for this through a default exception handler.
//! When an exception is hit, the default handler will trigger a breakpoint and in this debugging
//! context the stacked registers are accessible.
//!
//! In you run the example below, you'll be able to inspect the state of your
//! program under the debugger using these commands:
//! In you run the example below, you'll be able to inspect the state of your program under the
//! debugger using these commands:
//!
//! ``` text
//! (gdb) # Exception frame = program state during the crash
@@ -65,6 +64,7 @@
//!
//! extern crate cortex_m;
//! extern crate cortex_m_rt;
//! extern crate panic_abort; // panicking behavior
//!
//! use core::ptr;
//!

4
src/examples/_4_override_exception_handler.rs
View File

@@ -4,8 +4,7 @@
//!
//! [1]: https://docs.rs/cortex-m-rt/0.3.2/cortex_m_rt/macro.exception.html
//!
//! The default exception handler can be overridden using the
//! [`default_handler!`][2] macro
//! The default exception handler can be overridden using the [`default_handler!`][2] macro
//!
//! [2]: https://docs.rs/cortex-m-rt/0.3.2/cortex_m_rt/macro.default_handler.html
//!
@@ -19,6 +18,7 @@
//! extern crate cortex_m;
//! #[macro_use(exception)]
//! extern crate cortex_m_rt;
//! extern crate panic_abort; // panicking behavior
//!
//! use core::ptr;
//!

25
src/examples/_5_device.rs
View File

@@ -1,25 +1,22 @@
//! Using a device crate
//!
//! Crates generated using [`svd2rust`] are referred to as device crates. These
//! crates provides an API to access the peripherals of a device. When you
//! depend on one of these crates and the "rt" feature is enabled you don't need
//! link to the cortex-m-rt crate.
//! Crates generated using [`svd2rust`] are referred to as device crates. These crates provides an
//! API to access the peripherals of a device. When you depend on one of these crates and the "rt"
//! feature is enabled you don't need link to the cortex-m-rt crate.
//!
//! [`svd2rust`]: https://crates.io/crates/svd2rust
//!
//! Device crates also provide an `interrupt!` macro to register interrupt
//! handlers.
//! Device crates also provide an `interrupt!` macro to register interrupt handlers.
//!
//! This example depends on the [`stm32f103xx`] crate so you'll have to add it
//! to your Cargo.toml.
//! This example depends on the [`stm32f103xx`] crate so you'll have to add it to your Cargo.toml.
//!
//! [`stm32f103xx`]: https://crates.io/crates/stm32f103xx
//!
//! ```
//! $ edit Cargo.toml && cat $_
//! $ edit Cargo.toml && tail $_
//! [dependencies.stm32f103xx]
//! features = ["rt"]
//! version = "0.8.0"
//! version = "0.9.0"
//! ```
//!
//! ---
@@ -31,9 +28,11 @@
//! #![no_std]
//!
//! extern crate cortex_m;
//! // extern crate cortex_m_rt; // included in the device crate
//! extern crate cortex_m_semihosting;
//! #[macro_use(exception, interrupt)]
//! extern crate stm32f103xx;
//! extern crate panic_abort; // panicking behavior
//!
//! use core::cell::RefCell;
//! use core::fmt::Write;
@@ -43,11 +42,9 @@
//! use cortex_m_semihosting::hio::{self, HStdout};
//! use stm32f103xx::Interrupt;
//!
//! static HSTDOUT: Mutex<RefCell<Option<HStdout>>> =
//! Mutex::new(RefCell::new(None));
//! static HSTDOUT: Mutex<RefCell<Option<HStdout>>> = Mutex::new(RefCell::new(None));
//!
//! static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> =
//! Mutex::new(RefCell::new(None));
//! static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> = Mutex::new(RefCell::new(None));
//!
//! fn main() {
//! let global_p = cortex_m::Peripherals::take().unwrap();

14
src/examples/_6_allocator.rs
View File

@@ -1,7 +1,6 @@
//! How to use the heap and a dynamic memory allocator
//!
//! This example depends on the alloc-cortex-m crate so you'll have to add it
//! to your Cargo.toml:
//! This example depends on the alloc-cortex-m crate so you'll have to add it to your Cargo.toml:
//!
//! ``` text
//! # or edit the Cargo.toml file manually
@@ -13,8 +12,8 @@
//! ```
//!
//! #![feature(alloc)]
//! #![feature(used)]
//! #![feature(global_allocator)]
//! #![feature(used)]
//! #![no_std]
//!
//! // This is the allocator crate; you can use a different one
@@ -24,26 +23,27 @@
//! extern crate cortex_m;
//! extern crate cortex_m_rt;
//! extern crate cortex_m_semihosting;
//! extern crate panic_abort; // panicking behavior
//!
//! use core::fmt::Write;
//!
//! use alloc_cortex_m::CortexMHeap;
//! use cortex_m::asm;
//! use cortex_m_semihosting::hio;
//! use alloc_cortex_m::CortexMHeap;
//!
//! #[global_allocator]
//! static ALLOCATOR: CortexMHeap = CortexMHeap::empty();
//!
//! extern "C" {
//! static mut _sheap: u32;
//! static mut _eheap: u32;
//! }
//!
//! const HEAP_SIZE: usize = 1024; // in bytes
//!
//! fn main() {
//! // Initialize the allocator
//! let start = unsafe { &mut _sheap as *mut u32 as usize };
//! let end = unsafe { &mut _eheap as *mut u32 as usize };
//! unsafe { ALLOCATOR.init(start, end - start) }
//! unsafe { ALLOCATOR.init(start, HEAP_SIZE) }
//!
//! // Growable array allocated on the heap
//! let xs = vec![0, 1, 2];

30
src/lib.rs
View File

@@ -3,10 +3,10 @@
//! # Dependencies
//!
//! - Nightly Rust toolchain newer than `nightly-2018-04-08`: `rustup default nightly`
//! - ARM linker: `sudo apt-get install binutils-arm-none-eabi` (on Ubuntu)
//! - Cargo `clone` subcommand: `cargo install cargo-clone`
//! - GDB: `sudo apt-get install gdb-arm-none-eabi` (on Ubuntu)
//! - OpenOCD: `sudo apt-get install OpenOCD` (on Ubuntu)
//! - [Optional] ARM linker: `sudo apt-get install binutils-arm-none-eabi` (on Ubuntu)
//! - [Optional] Cargo `add` subcommand: `cargo install cargo-edit`
//!
//! # Usage
@@ -47,13 +47,14 @@
//! files.
//!
//! ``` text
//! $ edit memory.x && cat $_
//! $ cat >memory.x <<'EOF'
//! MEMORY
//! {
//! /* NOTE K = KiBi = 1024 bytes */
//! FLASH : ORIGIN = 0x08000000, LENGTH = 256K
//! RAM : ORIGIN = 0x20000000, LENGTH = 40K
//! }
//! EOF
//! ```
//!
//! 5) Optionally, set a default build target
@@ -87,7 +88,6 @@
//! 8) Build the application
//!
//! ``` text
//! $ # NOTE this command requires `arm-none-eabi-ld` to be in $PATH
//! $ cargo build --release
//!
//! $ # sanity check
@@ -113,6 +113,26 @@
//! Tag_ABI_FP_16bit_format: IEEE 754
//! ```
//!
//! **NOTE** By default Cargo will use the LLD linker shipped with the Rust toolchain. If you
//! encounter any linking error try to switch to the GNU linker by modifying the `.cargo/config`
//! file as shown below:
//!
//! ``` text
//! runner = 'arm-none-eabi-gdb'
//! rustflags = [
//! "-C", "link-arg=-Tlink.x",
//! - "-C", "linker=lld",
//! - "-Z", "linker-flavor=ld.lld",
//! - # "-C", "linker=arm-none-eabi-ld",
//! - # "-Z", "linker-flavor=ld",
//! + # "-C", "linker=lld",
//! + # "-Z", "linker-flavor=ld.lld",
//! + "-C", "linker=arm-none-eabi-ld",
//! + "-Z", "linker-flavor=ld",
//! "-Z", "thinlto=no",
//! ]
//! ```
//!
//! 9) Flash the program
//!
//! ``` text
@@ -165,7 +185,7 @@
//! Compiling demo v0.1.0 (file:///home/japaric/tmp/demo)
//! error: linking with `arm-none-eabi-ld` failed: exit code: 1
//! |
//! = note: "arm-none-eabi-ld" "-L" (..)
//! = note: "lld" "-L" (..)
//! = note: arm-none-eabi-ld: address 0xbaaab838 of hello section `.text' is ..
//! arm-none-eabi-ld: address 0xbaaab838 of hello section `.text' is ..
//! arm-none-eabi-ld:
@@ -184,7 +204,7 @@
//! ``` text
//! $ cargo build
//! (..)
//! Compiling cortex-m-semihosting v0.1.3
//! Compiling cortex-m-semihosting v0.2.0
//! error[E0463]: can't find crate for `std`
//!
//! error: aborting due to previous error